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Parent Node(s):
VERIFICATION
A (computer) model is said to be verified if it
behaves in the way that the model builder wanted it to behave.
This means that the instructions are correct and have been
properly programmed. One check for verification is to hold some
of the variables constant to determine whether the output changes
in anticipated ways as other variables are changed. Another
typical check is to test how the model behaves in limit
situations. Compare: validation (IIASA)
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